Fabrication method for IC-oriented Si single-electron transistors

Author

Ono, Yukinori ; Takahashi, Yasuo ; Yamazaki, Kenji ; Nagase, Masao ; Namatsu, Hideo ; Kurihara, Kenji ; Murase, Katsumi

Author_Institution

NTT Basic Res. Labs., Kanagawa, Japan

Volume

47

Issue

1

fYear

2000

fDate

1/1/2000 12:00:00 AM

Firstpage

147

Lastpage

153

Abstract

A new fabrication method for Si single-electron transistors (SETs) is proposed. The method applies thermal oxidation to a Si wire with a fine trench across it on a silicon-on-insulator substrate. During the oxidation, the Si wire with the fine trench is converted, in a self-organized manner, into a twin SET structure with two single-electron islands, one along each edge of the trench, due to position-dependent oxidation-rate modulation caused by stress accumulation. Test devices demonstrated, at 40 K, that the twin SET structure can operate as two individual SET´s. Since the present method produces two SET´s at the same time in a tiny area, it is suitable for integrating logic circuits based on pass-transistor type logic and CMOS-type logic, which promises to lead to the fabrication of single-electron logic LSIs

Keywords

CMOS logic circuits; SIMOX; elemental semiconductors; nanotechnology; oxidation; semiconductor quantum dots; silicon; single electron transistors; CMOS-type logic; Si; fabrication method; fine trench; pass-transistor type logic; position-dependent oxidation-rate modulation; single-electron islands; single-electron transistors; stress accumulation; thermal oxidation; twin SET structure; Fabrication; Logic circuits; Logic devices; Logic functions; Oxidation; Quantum dots; Silicon on insulator technology; Single electron devices; Single electron transistors; Wire;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.817580

Filename

817580