DocumentCode :
1291520
Title :
Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume :
19
Issue :
10
fYear :
2011
Firstpage :
1907
Lastpage :
1911
Abstract :
We define the strength of a test for transition faults based on the number of fault effects that can disappear without causing the test to lose the detection of target faults. The removal of fault effects represents the uncertainty created by pattern-dependent effects that can slow-down or speed-up signal-transitions, thus causing fault effects predicted by logic-level simulation to disappear. A test set that consists of higher-strength tests is less susceptible to these effects. We demonstrate that a transition fault test set with higher-strength tests also detects more path delay faults, which represent delay defects that were not targeted during test generation.
Keywords :
automatic test pattern generation; logic simulation; logic testing; fault effect removal; full-scan circuits; logic-level simulation; pattern-dependent effects; quality metric; target fault detection; test generation; test strength; transition fault test set; Circuit faults; Circuit testing; Computational modeling; Delay; Electrical fault detection; Fault detection; Predictive models; Robustness; Timing; Uncertainty; Broadside tests; path delay faults; scan circuits; test generation; transition faults;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2010.2057459
Filename :
5545494
Link To Document :
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