Circuit design for nuclear radiation test of CMOS multiplier chips

The design of a microprocessor-based electronic circuit to be used in testing the effects of nuclear radiation on a CMOS 8×8 multiplier chips is described. The multiplier chip undergoing testing is attached to a DUT (device under test) board which is enclosed in a metal container. The container is then lowered to the cobalt 60 radiation source located at the bottom of a 15-ft deep pool. The in-source test board containing the multiplier chip is attached to an Intel 8085-based, single-board microcomputer (SDK-85) by a 30-ft multiconductor diode. Doses of gamma-ray radiation from cobalt 60 are applied in steps at increasing quantities until the multipliers chip, which is tested between doses, begins to malfunction. An 8085 assembly language program is used for functional testing of the multiplier. The leakage current and the propagation delay time are also measured between doses.