Title :
Silicon compilation based on a data-flow paradigm
Author :
Jhon, Chu S. ; Sobelman, Gerald E. ; Krekelberg, David E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., IA, USA
fDate :
5/1/1985 12:00:00 AM
Abstract :
Presents the fundamental ideas and techniques for an approach to silicon compilation that is based on a data-flow paradigm. Data-flow graphs are discussed, and their relationship to the behavior of digital systems is established. The syntax and semantics of a particular data-flow language, YASC, are then presented. Finally, the silicon compilation process is discussed, with emphasis on the relationship between the data-flow specification and its logic-level realization. Both synchronous and self-timed implementations are considered.
Keywords :
circuit layout CAD; digital integrated circuits; logic CAD; YASC; circuit layout CAD; data-flow language; data-flow paradigm; digital systems; logic CAD; logic-level realization; self-timed implementations; silicon compilation; CMOS integrated circuits; Floors; Generators; Layout; Receivers; Silicon; Transmitters;
Journal_Title :
Circuits and Devices Magazine, IEEE
DOI :
10.1109/MCD.1985.6311967
