• DocumentCode
    1292529
  • Title

    Point defect yield model for wafer scale integration

  • Author

    Ketchen, Mark B.

  • Author_Institution
    IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
  • Volume
    1
  • Issue
    4
  • fYear
    1985
  • fDate
    7/1/1985 12:00:00 AM
  • Firstpage
    24
  • Lastpage
    34
  • Abstract
    Yield projections are a primary consideration in wafer scale integration. The author develops a point defect yield model for a two-way redundancy scheme appropriate for random logic. The model assumes that the fault-causing defects are randomly distributed locally but that the defect density can vary across a wafer as well as from one wafer to another. Examples are given to illustrate the strong dependence of the results on clustering of defects and on the redundancy partitioning. The importance of the distinction between on-wafer and wafer-to-wafer variations in defect density is demonstrated. Complications associated with the occurrence of small numbers of highly correlated defects are discussed.
  • Keywords
    integrated circuit technology; redundancy; semiconductor device models; IC technology; WSI; defect density; highly correlated defects; point defect yield model; random logic; redundancy partitioning; two-way redundancy scheme; wafer scale integration; yield projections; Circuit faults; Distribution functions; Equations; Fabrication; Redundancy; Semiconductor device modeling; Wafer scale integration;
  • fLanguage
    English
  • Journal_Title
    Circuits and Devices Magazine, IEEE
  • Publisher
    ieee
  • ISSN
    8755-3996
  • Type

    jour

  • DOI
    10.1109/MCD.1985.6311990
  • Filename
    6311990