A model for estimating power dissipation in a class of DSP VLSI chips

A high-level power dissipation model for filter- and transform-type digital signal processing (DSP) algorithms implemented using linearly connected multiply-add-based processing elements is presented. Exploration of alternative algorithms, architectures, and design styles for a given signal processing task in terms of high-level parameters is possible using this model. It is shown that there is often an optimal selection of the number and type of time-shared processing elements for VLSI implementation that minimizes the overall power dissipation. A major application of the proposed model is to make quantitative evaluations for exploration of alternative DSP algorithms and architectures. When combined with previously developed area-time metrics, the proposed power dissipation model permits a more realistic evaluation of new and existing circuit solutions to DSP tasks