Design methodology of CMOS algorithmic current A/D converters in view of transistor mismatches

The CMOS algorithmic current A/D converter is analyzed. with emphasis on the modeling and quantitative description that relate the accuracy of the converter to the transistor mismatch and the reference current of the converter. This leads to an inequality for determining the optimum sizes of the devices and the value of the reference current. It is shown that the area of the converter can be significantly reduced by scaling the devices per stage, without loss of accuracy and without an increase of the reference current. Design strategies of the converter are demonstrated by an example for an 8-b A/D converter. Inherent error sources such as offset and glitching are also considered. Simple means to solve these problems are proposed