Decomposition of binary integers into signed power-of-two terms

Previous work has shown that approximation of digital filter coefficients using sums of signed power-of-two terms yields significant area/speed advantages in custom implementations, at the expense of a slight frequency response deterioration. The completeness, uniqueness, and resolving power of signed powers-of-two representations are studied, and circuits for extracting a prescribed number of signed power-of-two terms whose sum is the closest approximation to a given integer are presented. Examples of implementation of these circuits in a CMOS process are given