Title :
A CMOS analog timing recovery circuit for PRML detectors
Author :
Roo, Pierte ; Spencer, Richard R. ; Hurst, Paul J.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
Abstract :
A fully integrated analog timing recovery circuit for partial-response maximum-likelihood (PRML) detectors for digital magnetic storage is described. The circuit uses a decision-directed minimum mean-squared error (MMSE) algorithm and achieves phase acquisition within 100-bit periods at a maximum speed of 180 Mb/s. It dissipates 76 mW from a single 3.3-V supply and has an active die area of 1.8 mm/sup 2/ in a 1.2-/spl mu/m CMOS process. At 180 Mb/s, the rms clock fitter is 15 ps and peak-to-peak jitter is 97 ps. The test results demonstrate the feasibility of an analog CMOS implementation of decision-directed MMSE timing recovery for PRML detectors.
Keywords :
CMOS analogue integrated circuits; digital magnetic recording; least mean squares methods; maximum likelihood detection; partial response channels; synchronisation; timing jitter; 1.2 micron; 180 Mbit/s; 3.3 V; 76 mW; CMOS analog timing recovery circuit; decision-directed minimum mean-squared error algorithm; digital magnetic storage; jitter; partial-response maximum-likelihood detector; CMOS analog integrated circuits; CMOS process; Clocks; Detectors; Jitter; Magnetic circuits; Magnetic memory; Maximum likelihood detection; Testing; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
