Title :
Single-ended SRAM with high test coverage and short test time
Author :
Wang, Chua-Chin ; Wu, Chi-Feng ; Hwang, Rain-Ted ; Kao, Chia-Hsiung
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
The advantages of low power dissipation and smaller chip area for single-ended SRAMs are well known. In this paper, we present the configuration and test strategy of a single-ended, six-transistor SRAM. The benefits of short test time, no retention test, and high test coverage are verified. The goals of low power, high quality control, and short test time of the full CMOS SRAM can be achieved.
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit testing; CMOS chip area; power dissipation; quality control; single-ended SRAM; test coverage; test time; Bridge circuits; Circuit faults; Circuit testing; Costs; Electrical fault detection; Fault detection; Power supplies; Random access memory; Voltage; Writing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
