Title :
Statistical static timing analysis using a skew-normal canonical delay model
Author :
Vijaykumar, M. ; Vasudevan, Vidya
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol. Madras, Chennai, India
Abstract :
In its simplest form, a parameterized block based statistical static timing analysis (SSTA) is performed by assuming that both gate delays and the arrival times at various nodes are Gaussian random variables. These assumptions are not true in many cases. Quadratic models are used for more accurate analysis, but at the cost of increased computational complexity. In this paper, we propose a model based on skew-normal random variables. It can take into account the skewness in the gate delay distribution as well as the nonlinearity of the MAX operation. We derive analytical expressions for the moments of the MAX operator based on the conditional expectations. The computational complexity of using this model is marginally higher than the linear model based on Clark´s approximations. The results obtained using this model match well with Monte-Carlo simulations.
Keywords :
Monte Carlo methods; approximation theory; computational complexity; delay circuits; random processes; statistical analysis; timing circuits; Clark approximation; Gaussian random variable; MAX operation; Monte-Carlo simulation; SSTA; computational complexity; gate delay; parameterized block; quadratic model; skew-normal canonical delay model; skew-normal random variable; statistical static timing analysis; Computational modeling; Delays; Integrated circuit modeling; Logic gates; Monte Carlo methods; Random variables; Standards;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
Conference_Location :
Dresden
DOI :
10.7873/DATE.2014.271