Acquisition time minimisation techniques for high-speed analogue signal processing

Acquisition time minimisation techniques using a two-stage amplifier for high-speed analogue signal processing in mixed-mode circuits are presented. The proposed techniques reduce overshoots and undershoots of the amplifier by adjusting its transconductance and achieve high-speed performance with little modification to the conventional amplifier architecture. The measured signal-to-noise-and-distortion ratio of the prototype 12 bit CMOS ADC based on the proposed techniques is improved by >5 dB at a 50 MHz sampling clock