Issues in the design of high performance SIMD architectures

Author

Allen, James D. ; Schimmel, David E.

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

Volume

7

Issue

8

fYear

1996

fDate

8/1/1996 12:00:00 AM

Firstpage

818

Lastpage

829

Abstract

In this paper, we consider the design of high performance SIMD architectures. We examine three mechanisms by which the performance of this class of machines may be improved, and which have been largely unexplored by the SIMD community. The mechanisms are pipelined instruction broadcast, pipelining of the PE architecture, and the introduction of a novel memory hierarchy in the PE address space which we denote the direct only data cache, (dod-cache). For each of the performance improvements, we develop analytical models of the potential speedup, and apply those models to real program traces obtained on a MasPar MP-2 system. In addition, we consider the impact of all improvements taken together

Keywords

cache storage; parallel architectures; performance evaluation; pipeline processing; MasPar MP-2 system; PE address space; PE architecture; analytical models; direct only data cache; high performance SIMD architectures; memory hierarchy; pipelined instruction broadcast; potential speedup; Analytical models; Broadcasting; Clocks; Delay; Helium; Integrated circuit packaging; Integrated circuit technology; Microprocessors; Packaging machines; Pipeline processing;

fLanguage

English

Journal_Title

Parallel and Distributed Systems, IEEE Transactions on

Publisher

ieee

ISSN

1045-9219

Type

jour

DOI

10.1109/71.532113

Filename

532113