• DocumentCode
    1293566
  • Title

    Inertial effect handling method for CMOS digital IC simulation

  • Author

    Juan-Chico, J. ; Bellido, M.J. ; Acosta, A.J. ; Valencia, M.

  • Author_Institution
    Inst. de Microelectron., Seville, Spain
  • Volume
    35
  • Issue
    23
  • fYear
    1999
  • fDate
    11/11/1999 12:00:00 AM
  • Firstpage
    2028
  • Lastpage
    2030
  • Abstract
    A method is presented for determining the occurrence of the inertial effect (pulse filtering) in CMOS digital logic gates to overcome the limitations of conventional approaches. It is based on accounting for individual input gate thresholds and a new scheduling mechanism, while maintaining compatibility with existing delay models
  • Keywords
    CMOS logic circuits; delays; integrated circuit modelling; logic gates; logic simulation; CMOS digital IC simulation; delay model; gate threshold; inertial effect; logic gate; pulse filtering; scheduling;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19991384
  • Filename
    819040
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1293566