Title :
A cost-effective multistage interconnection network with network overlapping and memory interleaving
Author :
Shin, Kang G. ; Liu, Jyh-Charn
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Abstract :
A cost-effective design is proposed for circuit-switching multistage interconnection networks (CSMINs). Increase of the network bandwidth and reduction of the network size (and thus low costs) are accomplished by network overlapping and memory interleaving (NOMI), instead of by increasing the number of switches or adding buffers. NOMI and its control principle are described on the basis of the structure and interconnection functions of CSMINs. Detailed accounts of both the network design and the drastic reduction in hardware costs are given. The impact of NOMI on system performance is also analyzed.
Keywords :
distributed processing; multiprocessing systems; switching networks; CSMINs; NOMI; circuit-switching multistage interconnection networks; network bandwidth; network overlapping and memory interleaving; network size; system performance; Bandwidth; Logic gates; Multiplexing; Multiprocessing systems; Multiprocessor interconnection; Switches; Switching circuits; Asynchronous and synchronous multiplexing; bandwidth; blocking factor; circuit switching; memory cluster; multistage interconnection network; network overlapping and memory interleaving; pass rate; processor cluster;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1985.6312208
