DocumentCode
129455
Title
Predictive parallel event-driven HDL simulation with a new powerful prediction strategy
Author
Seiyang Yang ; Jaehoon Han ; Doowhan Kwak ; Namdo Kim ; Daeseo Cha ; Junhyuck Park ; Kim, Jung-Ho
Author_Institution
Dept. of Comput. Eng., Pusan Nat. Univ., Busan, South Korea
fYear
2014
fDate
24-28 March 2014
Firstpage
1
Lastpage
3
Abstract
Traditional parallel event-driven HDL simulation methods suffer heavy synchronization & communication overhead for timely transferring the signal data among local simulators, which could easily nullify most of the expected simulation speed-up from parallelization. A new predictive parallel event-driven HDL simulation as a new promising approach had been proposed for enhancing simulation performance. In this paper, we have further enhanced this noble parallel simulation method for a series of not only timing, but also function oriented design changes with a new powerful prediction strategy. Experimentation with real SOC designs from industry has been performed for actual design changes, and shown the effectiveness of the enhanced approach.
Keywords
hardware description languages; integrated circuit design; synchronisation; system-on-chip; SOC designs; communication overhead; function oriented design; heavy synchronization; local simulators; parallel simulation; powerful prediction strategy; predictive parallel event-driven HDL simulation; signal data; Accuracy; Computational modeling; Data models; Hardware design languages; Logic gates; Predictive models; Timing; EDA; SOC; parallel event-driven simulation; simulation; verification;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
Conference_Location
Dresden
Type
conf
DOI
10.7873/DATE.2014.329
Filename
6800530
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