Current-density centric logical effort delay model for high-speed current-mode logic circuits

A simple yet accurate delay model based on the method of logical effort is presented for the analysis of high-speed current-mode logic (CML) circuits. The model describes the logical effort of a CML gate in terms of its operating current density normalised to the characteristic current density that yields peak transistor cutoff frequency (fT). Since the latter remains largely invariant over technology nodes as a result of constant-field scaling, the proposed logical effort model quantifies the effect of gate sizing, biasing and loading to simplify delay analysis for CML gates.