Title :
Exploiting STT-NV technology for reconfigurable, high performance, low power, and low temperature functional unit design
Author :
Ashammagari, Aditya R. ; Mahmoodi, Hamid ; Homayoun, Houman
Author_Institution :
Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA
Abstract :
Unavailability of functional units and their unequal activity makes performance bottlenecks and thermal hot spot units in general-purpose processors. We propose to use reconfigurable functional units to overcome these challenges. A selected set of complex functional units that might be underutilized, such as a multiplier and divider, are realized in a time-multiplexed fashion using a shared programmable Look Up Table (LUT) based fabric. This allows for run-time reconfiguration and migration of their activity. LUT based implementation also allows under-utilized functional units to be dynamically reconfigured to the functional units that have a performance bottleneck and hence improving performance. The programmable LUTs are realized using Spin Transfer Torque (STT) Magnetic technology (also called STT-NV) due to its zero leakage and CMOS compatibility. The results show significant performance improvement of 16% on average across standard benchmarks, when replacing CMOS multiplier and divider with reconfigurable STT-NV LUT counterpart. In addition, reconfiguration reduces the maximum temperature of functional units by up to 27°C and almost eliminates the thermal variation across them. This comes with small power overhead and no area impact.
Keywords :
embedded systems; low-power electronics; magnetoelectronics; microprocessor chips; table lookup; thermal management (packaging); CMOS compatibility; CMOS divider; CMOS multiplier; STT-NV technology; high performance functional unit design; low power functional unit design; low temperature functional unit design; reconfigurable functional unit design; run time reconfiguration; shared programmable look up table; spin transfer torque magnetic technology; zero leakage; Adders; Benchmark testing; CMOS integrated circuits; CMOS technology; Magnetic tunneling; Program processors; Table lookup; STT-NV logic; divider; functional units; low power; low temperature; multiplier; reconfigurable architecture;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
Conference_Location :
Dresden
DOI :
10.7873/DATE.2014.348