Set of self-timed latches for high-speed VLSI

A set of novel self-timed latches is introduced and analysed. These latches have no back-to-back connection as in conventional self-timed latches, and both inverting and noninverting outputs are evaluated simultaneously leading to higher operating frequencies. A novel type of cross-coupled inverter used in the proposed circuits implements static operation without the signal fighting with the main driver during signal transition. The power consumption of these latches is also comparable to, or less than, that of conventional circuits. The proposed latches are designed using a 0.35 μm CMOS technology. The comparison results indicate that the proposed active-low self-timed latch (ALSTL) improves speed by 22-34% over the conventional NAND SR latch, while for the active-high self-timed latch (AHSTL) the speed improvements are 20-35% with less power as compared to the corresponding NOR SR latch