A Parallel-Segmented Monolithic Step-Up Transformer

This letter proposes a parallel-segmentation method of a step-up transformer that simultaneously improves the impedance transformation ratio and passive efficiency. A corresponding scalable segmentation-based model is also developed on a silicon substrate case. Implementation of the proposed transformer using 0.18 μm CMOS technology successfully demonstrated impedance transformation from 50 Ω to 5.3 Ω with a minimum insertion loss of 1.52 dB at 1.7 GHz. Self-inductance of 1.4 and 4.8 nH, and quality factor of 7.6 and 6.8, were obtained for primary and secondary windings, respectively. Results of the measurement of the transformer show high agreement with the proposed model and verify the accuracy of the physical behavior of the model within the frequency of interest.