DocumentCode :
1296145
Title :
The Improvement of High- 
/Metal Gate pMOSFET Performance and Reliability Using Optimized Si Cap/SiGe Channel Structure
Author :
Yeh, Wen-Kuan ; Chen, Yu-Ting ; Huang, Fon-Shan ; Hsu, Chia-Wei ; Chen, Chun-Yu ; Fang, Yean-Kuen ; Gan, Kwang-Jow ; Chen, Po-Ying
Author_Institution :
Dept. of Electr. Eng., Nat. Univ. of Kaohsiung, Kaohsiung, Taiwan
Volume :
11
Issue :
1
fYear :
2011
fDate :
3/1/2011 12:00:00 AM
Firstpage :
7
Lastpage :
12
Abstract :
The impact of the Si cap/SiGe layer on the Hf-based high-k /metal gate SiGe channel pMOSFET performance and reliability has been investigated. We proposed an optimized strain SiGe channel with a Si cap layer to overcome the Ge diffusion and confine the channel carriers in the strained SiGe layer without the formation of a significant parasitic channel at the interface. With this optimized Si/SiGe stack channel, a high-performance Hf-based high-k/metal gate SiGe pMOSFET can be obtained with an appropriate VTH (~0.3 V), low C -V hysteresis ( <; 5 mV), and better ION - IOFF , VTH rolloff, and VTH stability. By the way, the related interface trap density in the high-k gate stack layer can also be reduced, thus improving the device´s NBTI and HCI stressing-induced reliability.
Keywords :
Ge-Si alloys; MOSFET; hafnium; high-k dielectric thin films; semiconductor device reliability; semiconductor materials; silicon; Hf; SiGe; channel carriers; high-k gate stack layer; high-k-metal gate pMOSFET; interface trap density; negative bias temperature instability; parasitic channel; stressing-induced reliability; High-$k$
fLanguage :
English
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
Publisher :
ieee
ISSN :
1530-4388
Type :
jour
DOI :
10.1109/TDMR.2010.2065806
Filename :
5549876
Link To Document :
