Title :
The TigerSHARC DSP architecture
Author :
Fridman, Jose ; Greenfield, Zvi
Author_Institution :
Analog Devices Inc., Norwood, MA, USA
Abstract :
This highly parallel DSP architecture based on a short-vector memory system incorporates techniques found in general-purpose computing. It promises sustained performance close to its peak computational rates of 900 MFLOPS (32-bit floating-point) or 3.6 BOPS (16-bit fixed-point)
Keywords :
digital signal processing chips; memory architecture; parallel architectures; 900 MFLOPS; DSP architecture; TigerSHARC; short-vector memory system; sustained performance; Computer architecture; Concurrent computing; Digital signal processing; Digital signal processing chips; Filtering algorithms; Finite impulse response filter; Floating-point arithmetic; IIR filters; Memory architecture; Signal processing algorithms;
Journal_Title :
Micro, IEEE
