DocumentCode
1296204
Title
Dual- 
Spacer Device Architecture for the Improvement of Performance of Silicon n-Channel Tunnel FETs
Author
Virani, Hasanali G. ; Adari, Rama Bhadra Rao ; Kottantharayil, Anil
Author_Institution
Dept. of Electr. Eng., Indian Inst. of Technol. Bombay, Mumbai, India
Volume
57
Issue
10
fYear
2010
Firstpage
2410
Lastpage
2417
Abstract
A dual-k spacer concept is proposed and evaluated in underlap and nonunderlap n-channel silicon tunnel field-effect transistors (FETs) for the first time using extensive device simulations. The dual-k spacer consists of an inner layer made of a high-k material and an outer layer made of a low-k material. It is shown that the dual-k spacer improves the performance of n-channel tunneling FETs and more so for the underlap structures. Performance improvements are illustrated and explained for SiO2, Al2O3, and HfO2 gate dielectrics. The structure is optimized for the on-state current without degrading the off-state current or the subthreshold slope.
Keywords
MOSFET; alumina; elemental semiconductors; hafnium compounds; high-k dielectric thin films; low-k dielectric thin films; silicon; silicon compounds; Al2O3; HfO2; Si; SiO2; device simulations; dual-k spacer device architecture; gate dielectrics; high-k material; low-k material; nonunderlap n-channel silicon tunnel field-effect transistors; silicon n-channel tunnel FET; underlap n-channel silicon tunnel field-effect transistors; CMOS technology; Dielectric materials; Dielectrics; FETs; High K dielectric materials; High-K gate dielectrics; Junctions; Leakage current; Logic gates; MOSFET circuits; Performance evaluation; Silicon; Thermal degradation; Tunneling; Band-to-band tunneling; high-k; subthreshold slope; tunnel field-effect transistor;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2010.2057195
Filename
5549884
Link To Document