Title :
Threshold Voltage Variations Make Full Adders Reliabilities Similar
Author :
Ibrahim, Walid ; Beiu, Valeriu
Author_Institution :
Fac. of IT, United Arab Emirates Univ., Abu Dhabi, United Arab Emirates
Abstract :
Addition is the most widely used arithmetic operation in digital applications. The reliability of full adder (FA) cells is crucial as they affect arithmetic logic and floating-point units, as well as cache/memory address calculations. This letter studies the reliability of five different FA designs. The analysis starts from the device level by estimating the effects threshold voltage variations will have on the reliability of scaled CMOS transistors. These estimations will then be used to calculate the reliability of the sum and carry_out signals. This letter will also briefly explore the effects of increasing the reliability of devices and of using gate-level redundancy schemes on the reliability of FAs.
Keywords :
CMOS logic circuits; adders; belief networks; floating point arithmetic; reliability; FA design reliability; FA reliability; addition; arithmetic logic; arithmetic operation; cache-memory address calculations; carry out signals; device reliability; digital applications; floating-point; full adder cells reliability; full adders reliabilities; gate-level redundancy schemes; scaled CMOS transistor reliability; threshold voltage variations; Adders; Bayesian methods; Birth disorders; CMOS integrated circuits; Digital arithmetic; Energy consumption; Floating-point arithmetic; Fluctuations; Integrated circuit reliability; Permission; Quantum cellular automata; Redundancy; Simulation; Threshold voltage; Very large scale integration; Adders; Bayesian network (BN); CMOS; reliability; threshold voltage; variations;
Journal_Title :
Nanotechnology, IEEE Transactions on
DOI :
10.1109/TNANO.2010.2066573
