Generating Cycle Time-Throughput Curves Using Effective Process Time Based Aggregate Modeling

In semiconductor manufacturing, cycle time-throughput (CT-TH) curves are often used for planning purposes. To generate CT-TH curves, detailed simulation models or analytical queueing approximations may be used. Detailed models require much development time and computational effort. On the contrary, analytical models, such as the popular closed-form queueing expression, may not be sufficiently accurate, in particular, for integrated processing equipment that have wafers of more than one lot in process. Recently, an aggregate simulation model representation of workstations with integrated processing equipment has been proposed. This aggregate model is a type of system with a workload-dependent process time distribution, which is obtained from lot arrival and departure events. This paper presents a first proof of concept of the method in semiconductor practice. We develop the required extensions to generate CT-TH curves for workstations in a semiconductor manufacturing environment where usually only a limited amount of arrival and departure data is available. We present a simulation and an industry case to illustrate the proposed method.