DocumentCode
1296685
Title
Fast quadratic increase of multiport-storage-cell area with port number
Author
Tatsumi, Y. ; Mattausch, H.J.
Author_Institution
Graduate Sch. of Adv. Sci. of Matter, Hiroshima Univ., Japan
Volume
35
Issue
25
fYear
1999
fDate
12/9/1999 12:00:00 AM
Firstpage
2185
Lastpage
2187
Abstract
It is shown that the space required for wordline/bitline routing leads to a quadratic multiport-storage-cell area increase with port number N, dominating from as little as N=2, N=6 for small ROM and large SRAM cell types, respectively. Larger N results in enormous area increases (e.g. by a factor of 80 for a 32-port SRAM)I making conventional multiport memories unacceptable for most practical applications
Keywords
integrated circuit layout; integrated memory circuits; network routing; read-only storage; ROM cell; SRAM cell; multiport memories; multiport-storage-cell area; port number; quadratic area increase; wordline/bitline routing;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19991511
Filename
820288
Link To Document