• DocumentCode
    1296744
  • Title

    Analogue CMOS vector normalisation circuit

  • Author

    Fikos, G. ; Siskos, S.

  • Author_Institution
    Dept. of Phys., Thessaloniki Univ., Greece
  • Volume
    35
  • Issue
    25
  • fYear
    1999
  • fDate
    12/9/1999 12:00:00 AM
  • Firstpage
    2197
  • Lastpage
    2198
  • Abstract
    A novel CMOS analogue circuit is proposed, which can be used to perform vector normalisation with respect to a Euclidean measure, with a bias circuit for all inputs and only four transistors per input. It is very fast, with <1% linearity error over a decade of the norm of the input vector
  • Keywords
    CMOS analogue integrated circuits; analogue processing circuits; Euclidean measure; analogue CMOS vector normalisation circuit; bias circuit; four-transistor cell; linearity error;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19991503
  • Filename
    820296
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1296744