Title :
Analogue CMOS vector normalisation circuit
Author :
Fikos, G. ; Siskos, S.
Author_Institution :
Dept. of Phys., Thessaloniki Univ., Greece
fDate :
12/9/1999 12:00:00 AM
Abstract :
A novel CMOS analogue circuit is proposed, which can be used to perform vector normalisation with respect to a Euclidean measure, with a bias circuit for all inputs and only four transistors per input. It is very fast, with <1% linearity error over a decade of the norm of the input vector
Keywords :
CMOS analogue integrated circuits; analogue processing circuits; Euclidean measure; analogue CMOS vector normalisation circuit; bias circuit; four-transistor cell; linearity error;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19991503
