High-performance bipolar technology for improved ECL power delay

Author

Warnock, J. ; Cressler, J.D. ; Jenkins, K.A. ; Stanis, C. ; Sun, J.Y.-C. ; Tang, D.D. ; Petrillo, E. ; Hu, C.K.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

12

Issue

6

fYear

1991

fDate

6/1/1991 12:00:00 AM

Firstpage

315

Lastpage

317

Abstract

A new shallow trench process for isolation of bipolar devices is shown to allow butting of the emitter-base junction to the field oxide edge, thereby greatly reducing the overall device size and parasitic capacitances. Emitter-coupled logic (ECL) ring-oscillator measurements demonstrate a significant performance leverage, where a delay of 75 ps is obtained at a power of 1.5 mW per gate (power-delay product of 112 fJ ), an improvement of 17% from the nonbutted case. More conventional nonbutted devices have been fabricated with dopant profiles tailored to reduce intrinsic and extrinsic capacitances. These high-performance designs achieve ECL gate delays as small as 26 ps at 5.3 mW, comparable to the fastest ECL delays reported to date.<>

Keywords

bipolar integrated circuits; emitter-coupled logic; integrated circuit technology; integrated logic circuits; 1.5 mW; 112 fJ; 26 ps; 5.3 mW; 75 ps; ECL gate delays; bipolar technology; butting emitter-base junction to field oxide; delay; dopant profiles tailored; extrinsic capacitances; high-performance designs; improved ECL power delay; isolation of bipolar devices; parasite capacitance reduction; performance leverage; power; power-delay product; ring-oscillator measurements; shallow trench process; size reduction; trench isolation; Circuits; Cutoff frequency; Delay; Design optimization; Fabrication; Hafnium; Isolation technology; Parasitic capacitance; Senior members; Sun;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.82072

Filename

82072