Matrix-Based Codes for Adjacent Error Correction

Memories are one of the most widely used elements in electronic systems, and their reliability when exposed to single events upsets (SEUs) has been studied extensively. As transistor sizes shrink, multiple cells upsets (MCUs) are becoming an increasingly important factor in the reliability of memories exposed to radiation effects. To address this issue, built-in current sensors (BICS) or Parity codes have recently been applied in conjunction with single error correction/double error detection (SEC-DED) codes to protect memories from MCUs. In this paper, this approach is taken one step further, proposing specific codes optimized to provide protection against errors in adjacent bits in memories. By exploiting the locality of errors within an MCU and the error detection and location capabilities of parity codes, the proposed codes result in both a better protection level and a reduced cost. This technique improves memory reliability by 675X compared to Hamming Codes (HC) and 38X the mean time to failure (MTTF) compared to Reed Muller Codes (RMC) for clustered MCUs.