High-performance energy-efficient D-flip-flop circuits

Author

Ko, Uming ; Balsara, Poras T.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

Volume

8

Issue

1

fYear

2000

Firstpage

94

Lastpage

98

Abstract

This paper investigates performance, power, and energy efficiency of several CMOS master-slave D-flip-flops (DFF´s). To improve performance and energy efficiency, a push-pull DFF and a push-pull isolation DFF are proposed. Among the five DFF´s compared, the proposed push-pull isolation circuit is found to be the fastest with the best energy efficiency. Effects of using a double-pass-transistor logic (DPL) circuit and tri-state push-pull driver are also studied. Last, metastability characteristics of the five DFP´s are also analyzed.

Keywords

CMOS logic circuits; circuit optimisation; circuit stability; finite state machines; flip-flops; logic design; low-power electronics; sequential circuits; CMOS master-slave flip-flops; D-flip-flop circuits; DPL circuit; FSM; control logic; double-pass-transistor logic circuit; energy-efficient flip-flop circuits; high-performance D-flip-flop circuits; low-power flip-flops; metastability characteristics; push-pull isolation type; push-pull type; tri-state push-pull driver; Clocks; Energy efficiency; Feedback; Inverters; Logic circuits; Metastasis; Microprocessors; Page description languages; Power dissipation; Registers;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.820765

Filename

820765