DocumentCode :
1299111
Title :
Use of a Contacted Buried 
Layer for Single Event Mitigation in 90 nm CMOS
Author :
DasGupta, Sandeepan ; Amusan, Oluwole A. ; Alles, Michael L. ; Witulski, Arthur F. ; Massengill, Lloyd W. ; Bhuva, Bharat L. ; Schrimpf, Ronald D. ; Reed, Robert A.
Author_Institution :
Electr. Eng. & Comput. Sci. Dept., Vanderbilt Univ., Nashville, TN, USA
Volume :
56
Issue :
4
fYear :
2009
Firstpage :
2008
Lastpage :
2013
Abstract :
3-D TCAD simulation results predict reduction in single event charge collection, transient pulse widths, and charge sharing in a 90 nm bulk twin well process CMOS by using a contacted n+ buried layer.
Keywords :
CMOS integrated circuits; buried layers; technology CAD (electronics); CMOS; TCAD simulation; contacted buried n+ layer; single event mitigation; size 90 nm; transient pulse widths; CMOS process; CMOS technology; Discrete event simulation; Doping; MOS devices; Pulse inverters; Pulse width modulation inverters; Radiation hardening; Space vector pulse width modulation; Substrates; Buried layer; TCAD; single event; substrate engineering;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/TNS.2008.2012344
Filename :
5204586
Link To Document :
