Wafer scale integration

The history of integrated circuit development has been one of continually decreasing feature size, accompanied by a much more gradual increase in chip dimensions. There are obvious limits to both of these trends. In the case of chip size, clearly, the limit is the whole wafer, offering a circuit area on a 15 cm wafer that is roughly 175 times larger than current VLSI chips. Such a step function in chip size offers a massive increase in potential functional complexity, but also implies a radical rethink of philosophy in design, fabrication, test and packaging. This article discusses the problems associated with the development of WSI technology and reviews some of the strategies that have been adopted in the pursuit of WSI sub-systems.