DocumentCode :
1299458
Title :
Hierarchical determination of precedence order and representation of digraphs
Author :
Inagaki, Takahiro ; Himmelblau, D.H.
Author_Institution :
Inst. of Information Sci. & Electronics, Univ. of Tsukuba, Ibaraki, Japan
Issue :
3
fYear :
1983
Firstpage :
406
Lastpage :
413
Abstract :
A new way is described via a linked records structure of establishing the precedence order among relations given by an acyclic digraph with Boolean AND or OR gates at some vertices. The proposed algorithm is illustrated by an application to modular instruction system, and contrasted with ISM.
Keywords :
directed graphs; digraphs; linked records structure; modular instruction system; precedence order; Cybernetics; Indexes; Logic gates; Memory management; Merging; Optimization; Sparse matrices;
fLanguage :
English
Journal_Title :
Systems, Man and Cybernetics, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9472
Type :
jour
DOI :
10.1109/TSMC.1983.6313172
Filename :
6313172
Link To Document :
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