• DocumentCode
    1299593
  • Title

    Latent damage investigation on lateral nonuniform charge generation and stress-induced leakage current in silicon dioxide subjected to high-field current impulse stressing

  • Author

    Chim, Wai-Kin ; Lim, Peng-Soon

  • Author_Institution
    Fac. of Eng., Nat. Univ. of Singapore, Singapore
  • Volume
    47
  • Issue
    2
  • fYear
    2000
  • fDate
    2/1/2000 12:00:00 AM
  • Firstpage
    473
  • Lastpage
    481
  • Abstract
    This paper reports on positive lateral nonuniform (LNU) charge generation in silicon dioxide, and its relationship to transient or AC stress-induced leakage current (SILC), for MOS capacitor devices subjected to high-field current impulse stressing using a transmission line pulsing technique. The formation of LNU charge was attributed to the localized injection of avalanche hot carriers from the silicon substrate together with the accompanying impact ionization within the oxide. The short stress pulse duration was identified as an important factor for the generation of LNU charge as a longer duration stress pulse or DC stressing gives rise to more uniform charge trapping. A model, consisting of several similar area and equivalent MOS capacitors connected in parallel, was used to explain the effect of LNU charge generation on the high-frequency capacitance-voltage curves. Electrical annealing results indicate that the positive LNU charge traps are located close to the silicon-oxide interface. The LNU charges are distributed with a certain minimum trap energy level which require a critical fluence or gate voltage to be applied before significant LNU charge annealing is observed. The positive LNU charges, which lower the energy levels of neutral traps, are responsible for the transient SILC observed in the thicker oxide devices
  • Keywords
    MOS capacitors; dielectric thin films; electron traps; electrostatic discharge; hole traps; hot carriers; impact ionisation; interface states; leakage currents; semiconductor device models; semiconductor device reliability; semiconductor-insulator boundaries; silicon compounds; AC SILC; ESD; HF C-V curves; HF capacitance-voltage curves; MOS capacitor devices; Si; Si substrate; Si-SiO2; Si-oxide interface; avalanche hot carriers; charge annealing; critical gate voltage; electrical annealing; high-field current impulse stressing; impact ionization; latent damage investigation; lateral nonuniform charge generation; localized injection; minimum trap energy level; model; neutral traps; positive charge generation; positive charge traps; stress-induced leakage current; transient SILC; transmission line pulsing technique; AC generators; Annealing; Energy states; Hot carriers; Leakage current; MOS capacitors; Power system transients; Silicon compounds; Stress; Transmission lines;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.822296
  • Filename
    822296