• DocumentCode
    1299698
  • Title

    VLSI implementation of 350 MHz 0.35 μm 8 bit merged squarer

  • Author

    Kolagotla, R.K. ; Griesbach, W.R. ; Srinivas, H.R.

  • Author_Institution
    Lucent Technol., Allentown, PA, USA
  • Volume
    34
  • Issue
    1
  • fYear
    1998
  • fDate
    1/8/1998 12:00:00 AM
  • Firstpage
    47
  • Lastpage
    48
  • Abstract
    The partial-products of a squarer are symmetric about the diagonal, and are typically folded and shifted to reduce the depth of the array. The authors describe a technique that further reduces the critical path by merging the partial-products along the diagonal with the rest of the folded array. An 8 bit squarer operates at 350 MHz in the Lucent 0.35 μm CMOS process
  • Keywords
    CMOS digital integrated circuits; VLSI; digital arithmetic; 0.35 micron; 350 MHz; 8 bit; Lucent CMOS process; VLSI implementation; merged squarer; partial-products;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19980057
  • Filename
    654510
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1299698