Title :
SET Emulation Considering Electrical Masking Effects
Author :
Entrena, Luis ; Valderas, Mario García ; Cardenal, Raúl Fernández ; García, Marta Portela ; Ongil, Celia López
Author_Institution :
Electron. Technol. Dept., Univ. Carlos III of Madrid, Leganes, Spain
Abstract :
A new approach is proposed for evaluating circuit robustness against Single Event Transients (SETs) through FPGA emulation. A voltage-time quantization model allows capturing circuit delays in the FPGA, including electrical masking effects. Experimental results demonstrate this approach improves SET fault injection rate by three orders of magnitude with respect to logic simulation and provides an accuracy close to analog simulation.
Keywords :
delays; field programmable gate arrays; masks; FPGA emulation; SET fault injection rate; analog simulation; circuit delays; circuit robustness; logic simulation; single event transient emulation; voltage-time quantization model; Circuit faults; Circuit simulation; Delay effects; Emulation; Error analysis; Field programmable gate arrays; Logic; Quantization; Single event upset; Transient analysis; Electrical masking; FPGA emulation; fault injection; single event transient (SET);
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2009.2013346
