Pulsewidth control loop in high-speed CMOS clock buffers

In high-speed CMOS clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a multistage buffer because the circuit is not pure digital. Signal quality degradation is influenced by temperature and process deviation. In this paper, we propose a pulsewidth control loop to get required pulsewidth. To investigate the loop stability, a linearized small signal analysis model is used. Results of SPICE simulation show that the pulsewidth can be well controlled if the loop parameters are properly chosen. The pulsewidth can be easily adjusted to a desired value by sizing the ratio of transistor sizes in the current mirror of charge pump.