Title :
Speed and power scaling of SRAM´s
Author :
Amrutur, Bharadwaj S. ; Horowitz, Mark A.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
Simple models for the delay, power, and area of a static random access memory (SRAM) are used to determine the optimal organizations for an SRAM and study the scaling of their speed and power with size and technology. The delay is found to increase by about one gate delay for every doubling of the RAM size up to 1 Mb, beyond which the interconnect delay becomes an increasingly significant fraction of the total delay. With technology scaling, the nonscaling of threshold mismatches in the sense amplifiers is found to significantly impact the total delay in generations of 0.1 /spl mu/m and below.
Keywords :
SRAM chips; delays; integrated circuit interconnections; memory architecture; 0.1 micron; RAM size; SRAMs; area; gate delay; interconnect delay; power; sense amplifiers; threshold mismatches; total delay; Analytical models; Decoding; Delay effects; Delay estimation; Energy consumption; Integrated circuit interconnections; Random access memory; Read-write memory; SRAM chips; Transistors;
Journal_Title :
Solid-State Circuits, IEEE Journal of
