Title :
A charge-trapping-based technique to design low-voltage BiCMOS logic circuits
Author :
Seng, Yeo Kiat ; Rofail, Samir S.
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
fDate :
1/1/1998 12:00:00 AM
Abstract :
New BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits´ performances are comparatively evaluated with the CMOS and that of the recently reported circuits. The proposed circuits were fabricated using a standard 0.8-μm BiCMOS process. The experimental results obtained from the fabricated chip have verified the functionality of the proposed logic gates
Keywords :
BiCMOS digital integrated circuits; BiCMOS logic circuits; adders; logic design; logic gates; 0.8 micron; LV BiCMOS logic circuits; XOR gate; adder; charge-trapping-based technique; low-voltage logic circuit design; submicron technologies; Adders; BiCMOS integrated circuits; CMOS logic circuits; Circuit simulation; Degradation; Logic circuits; Logic gates; Propagation delay; Very large scale integration; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
