Title :
Estimation of Trapped Charge Density in SONOS Flash Memory Using a Parallel Capacitor Model
Author :
Hua-Min Li ; Gang Zhang ; Won Jong Yoo
Author_Institution :
Dept. of Nanosci. & Technol., Sungkyunkwan Univ., Suwon, South Korea
Abstract :
This paper proposes a model established using the parallel connection of MOS and floating-gate MOS capacitors to examine the electric properties of polysilicon-oxide-nitride-oxide-silicon (SONOS) Flash memory in both the fresh and programmed states. A linear relationship between threshold voltage shift and effective trapped charge density was revealed via the threshold electric field. The simulation of the channel current was given based on our model, being in agreement with the experimental results for both forward and reverse read modes. The model and theory make an easy and time-saving approach to comprehensively analyze the trapped charge and its effect on other electric properties, e.g., electric field, oxide capacitance, and charge distribution, contributing to the control of the write/erase operation, the optimization of the device structure, and the characteristics of the retention properties in SONOS Flash memory.
Keywords :
MOS capacitors; MOS memory circuits; flash memories; SONOS flash memory; charge distribution; device structure optimization; electric field; electric property; floating-gate MOS capacitors; oxide capacitance; parallel capacitor model; polysilicon-oxide-nitride-oxide-silicon flash memory; reverse read modes; threshold electric field; time-saving approach; trapped charge density estimation; Capacitance; Capacitors; Charge carrier processes; Logic gates; SONOS devices; Substrates; Threshold voltage; Polysilicon–oxide–nitride–oxide–silicon (SONOS); threshold electric field; threshold voltage shift; trapped charge density;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2011.2162730
