• DocumentCode
    1300939
  • Title

    Robust Fault Models Where Undetectable Faults Imply Logic Redundancy

  • Author

    Pomeranz, Irith ; Reddy, Sudhakar M.

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
  • Volume
    18
  • Issue
    8
  • fYear
    2010
  • Firstpage
    1230
  • Lastpage
    1234
  • Abstract
    We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy. The stuck-at fault model is robust, but other fault models such as certain bridging and interconnect open fault models are not. A robust fault model provides a mechanism to synthesize circuits in which all the target faults are detectable and 100% fault coverage is achievable. This is important since it provides a direct link between test quality and the circuit synthesis. We discuss robust fault models for bridging faults and interconnect open faults, and their use as part of a test generation process for a non-robust fault model.
  • Keywords
    circuit testing; fault tolerance; network synthesis; redundancy; circuit synthesis; logic redundancy; robust fault models; stuck-at fault model; test quality; undetectable faults; Bridging faults; interconnect open faults; logic redundancy; test generation; undetectable faults;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2009.2020592
  • Filename
    5208205