A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation

A 65 nm self-synchronous field programmable gate array (SSFPGA) with delay insensitive operation and pipeline granularity at the gate level, is shown to be robust to process voltage and temperature (PVT) variations. The proposed SSFPGA employs a 38 × 38 array of four-input, three-stage self-synchronous configurable logic blocks, with the introduction of a new dual tree-divider four-input, three-pipeline stage LUT to achieve a 2.97 GHz throughput at 1.2 V. Correct operation is measured with 500 mVp-p, 1.12 GHz externally introduced power supply noise at 1.2 V power supply, equivalent to 42% power supply bounce. Sensitivity against power supply noise frequency has been measured, and confirmed with simulation results to show a strong correlation with the average operating frequency. Correct operation was shown over 10 chips with 16% performance variation, with VDD change from 728 mV to 2 V, and temperature change from 0°C to 120°C, without tuning any input parameters such as clock frequency, supply voltages and biases. Results show the SSFPGA can adapt and is inherently robust to these variations with internal throughput measured from 300 MHz to 4.07 GHz, while maintaining correct operation. The operation under noisey power supply conditions is compared to a conventional synchronous FPGA, which show the SSFPGA has 4.2 times error free operation. The failure mode is also measured on the SSFPGA using an accelerated stress cycle between 0°C and 120°C at 2 V, showing the SSFPGA has 8% longer correct operation before chip malfunction past a 10% delay margin commonly used in synchronous systems.