Cascaded parallel oversampling sigma-delta modulators

Based on the well-known time-interleaved modulator (TIM), a new cascade-parallel architecture of oversampling sigma-delta analog-to-digital converters is proposed. While retaining the speed advantage of TIM, the new architecture gives a general method to effectively suppress the influence of circuit nonidealities, especially coefficient mismatches, on the converter´s resolution. Such influence is a serious problem in the practical realization of TIM. Simulation results of examples of both TIM and the new architecture are given for comparison. In addition to its improved performance, the new architecture turns out to be quite simple. Therefore it can be a practical approach to extend the use of sigma-delta analog-to-digital conversion to high-speed applications