• DocumentCode
    130140
  • Title

    Analysis and optimization of the system-level simulator

  • Author

    Liu Fang ; Zhang Shengbing ; Liu Yang ; Zhang Meng

  • Author_Institution
    Sch. of Comput. Sci. & Eng., Northwestern Polytech. Univ., Xi´an, China
  • fYear
    2014
  • fDate
    28-30 July 2014
  • Firstpage
    1020
  • Lastpage
    1024
  • Abstract
    Simulator is a software system running on the host and the behaviour of the simulated target architecture machine. It can explain and execute the executable program on the target architecture machine, while providing run-time instruction and event-related records, as well as the performance of statistical parameters of the target architecture machine. Systemlevel architecture simulator can be used as a virtual target machine running the software system can achieve the functional simulation of the single (multi) processor, system memory, cache, and an external device subsystem. The simulator is an important means for the processor architecture. Accurate simulation of the processor architecture can access and analyze the architecture parameters on the performance of the processor, to provide effective support for the architecture design space exploration. Simulator development purposes and a different focus, vary widely in speed, uses simulation target, degree of simulation. This article is based on the characteristics of different workloads to study the performance of several state-of-art system-level architecture simulators and focuses on the method that can improve the system performance significantly. We take SPLASH-2 as the benchmark to test the performance of these representative system-level architecture simulators. Finally we give a summary on the optimization methods of different kinds of simulators.
  • Keywords
    computer architecture; optimisation; performance evaluation; shared memory systems; simulation; SPLASH-2; architecture parameter analysis; event-related records; executable program; multiprocessor system; processor architecture; processor performance; run-time instruction; system memory; system-level simulator optimization; target architecture machine; Accuracy; Bandwidth; Benchmark testing; Educational institutions; Memory management; Prefetching; simulator performance; splash-2; system-level architecture simulators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Information and Automation (ICIA), 2014 IEEE International Conference on
  • Conference_Location
    Hailar
  • Type

    conf

  • DOI
    10.1109/ICInfA.2014.6932799
  • Filename
    6932799