Title :
Testing the interconnect of RAM-based FPGAs
Author :
Renovell, Michel ; Portal, Jean Michel ; Figueras, Joan ; Zorian, Yervant
Author_Institution :
LIRMM-UMII, Montpellier, France
Abstract :
Testing FPGAs before user programming can be an expensive procedure. Applying their general test configuration and test pattern generation methodology, the authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs
Keywords :
field programmable gate arrays; integrated circuit interconnections; integrated circuit testing; logic testing; FPGAs; RAM-based; interconnect; interconnect structure; test configuration; test pattern generation; test procedure; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Field programmable gate arrays; Flexible printed circuits; Integrated circuit interconnections; Manufacturing; Portals; Test pattern generators;
Journal_Title :
Design & Test of Computers, IEEE
