Title :
Estimation of Analog Parametric Test Metrics Using Copulas
Author :
Bounceur, Ahcène ; Mir, Salvador ; Stratigopoulos, Haralampos-G
Author_Institution :
Lab.-STICC Lab., Eur. Univ. of Brittany, Rennes, France
Abstract :
A new technique for the estimation of analog parametric test metrics at the design stage is presented in this paper. This technique employs the copulas theory to estimate the distribution between random variables that represent the performances and the test measurements of the circuit under test (CUT). A copulas-based model separates the dependencies between these random variables from their marginal distributions, providing a complete and scale-free description of dependence that is more suitable to be modeled using well-known multivariate parametric laws. The model can be readily used for the generation of an arbitrarily large sample of CUT instances. This sample is thereafter used for estimating parametric test metrics such as defect level (or test escapes) and yield loss. We demonstrate the usefulness of the proposed technique to evaluate a built-in-test technique for a radio frequency low noise amplifier and to set test limits that result in a desired tradeoff between test metrics. In addition, we compare the proposed technique with previous ones that rely on direct density estimation.
Keywords :
built-in self test; circuit testing; low noise amplifiers; parameter estimation; radiofrequency amplifiers; CUT; analog parametric test metric estimation design; arbitrarily large sample generation; built-in-test technique; circuit under test; copulas-based model; direct density estimation; distribution estimation; multivariate parametric law; radio frequency low noise amplifier; random variable; test measurement; Correlation; Estimation; Gaussian distribution; Integrated circuit modeling; Joints; Measurement; Random variables; Analog test; RF test; built-in test; copulas theory; mixed-signal test; nonparametric statistics; statistical modeling; test metrics estimation;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2011.2149522