Voltage-Driven Partial-RESET Multilevel Programming in Phase-Change Memories

In this paper, the feasibility of partial-RESET programming in phase-change memories is experimentally investigated by considering both the single-cell behavior and the effects of parameter spreads over a memory array. The aim of this paper is to highlight advantages and drawbacks of partial-RESET programming from the viewpoint of multilevel (ML) storage. Although high reproducibility of a partial-RESET programming curve of a single cell has been observed, the parameter spreads over the array imply the need for a program-and-verify (P&V) approach to achieve the necessary accuracy for ML storage. In order to demonstrate the feasibility of partial-RESET ML programming, 4 log-spaced levels within the available resistance window have been programmed by means of a staircase-up P&V algorithm.