Title :
Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance
Author :
Chen, Yiran ; Li, Hai ; Koh, Cheng-Kok ; Sun, Guangyu ; Li, Jing ; Xie, Yuan ; Roy, Kaushik
Author_Institution :
Seagate Technol., Bloomington, MN, USA
Abstract :
In this paper, we proposed a new adder design called variable-latency adder (VL-adder). This technique allows the adder to work at a lower supply voltage than that required by a conventional adder while maintaining the same throughput. The VL-adder design can be further modified to overcome the effects of negative bias temperature instability (NBTI) on circuit delay. By applying VL-adder concept to a 64-bit carry-select adder design, more than 40% energy saving is obtained when a similar throughput is maintained.
Keywords :
adders; digital arithmetic; integrated circuit design; logic design; IC design; NBTI tolerance; circuit delay; digital arithmetic; logic design; negative bias temperature instability; variable-latency adder designs; word length 64 bit; Adders; Circuits; Clocks; Delay; Negative bias temperature instability; Niobium compounds; Sun; Throughput; Titanium compounds; Very large scale integration; Digital arithmetic; IC design; logic design;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2009.2026280
