Novel architecture for ATM QoS management

A novel architecture and an enhanced approach to a flexible, starvation-free ATM QoS managing function is proposed. To meet the stringent timing constraint of the delay QoSs, both high-speed sorter and subtractor are exploited to sort the priority value as well as to process the priority value. The subtractive policy is used to prevent starvation and to assign the priority of each output queue. In addition, to prevent underflow of the priority value and to process the empty queue situation, both the renormalisation circuit and empty flag are exploited to perform the normalisation function. Simulation results show that the throughput of the enhanced architecture is more than 50 M output requests per second (21.2 Gbit/s for ATM cells) by using a 1.2 μm CMOS process. The proposed architecture can be cascadable, making it very suitable for complex QoS management