Title :
Statistical High-Level Synthesis under Process Variability
Author :
Xie, Yuan ; Chen, Yibo
Author_Institution :
Pennsylvania State Univ., PA, USA
Abstract :
CMOS process variability is a major challenge in deep-submicron SoC designs. The variations in transistor parameters are complicating both timing and power consumption prediction. This article surveys recent progress in the statistical high-level synthesis area.
Keywords :
CMOS digital integrated circuits; high level synthesis; logic design; statistical analysis; system-on-chip; CMOS process variability; deep-submicron SoC design; power consumption prediction; statistical high-level synthesis; system-on-chip; timing prediction; transistor parameter; Design methodology; Electronics industry; Graphics; High level synthesis; Manufacturing; Process design; Production; Productivity; Testing; Transistors; design and test; parametric yield; process variation; statistical high-level synthesis;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2009.85
